| General Information |
| Device Marking(TOP MARK) | 7371
&E&Z&3
| |
| Family Code | 0SB | |
| Package Type | SOIC | |
| Package Description | PDD STD_ 8-SOP-225 | |
| Pin Count | 8 | |
| FIT | 6.6 | |
| Maximum Reflow Temperature | 260C | |
| MSL Rating | 1| | |
| Restriction of Hazardous Substance |
| Standard Plating Finish | Matte Sn | |
| Base Metal/Leadframe Material | Copper,Iron,Zinc,Phosphorus,Silver | |
| Lead Pitch | 1270 | |
| Minimum Lead Spacing | 760 | |
| Die Fabrication |
| Fabrication Process Identifier | HDG4 | |
| Package Assembly* |
| Plating Finish Layer Thickness | 8.0um - 18um | |
| Thermal Impedance (Theta JA) | 200 | °C/Watt |
| Thermal Impedance (Theta JC) | 40 | °C/Watt |
| Moisture Sensitivity | 1 | |
| Electrical Test |
| ESD Human Body Model (HBM) | 2000 | V |
| ESD Charged Device Model (CDM) | 1000 | V |
