EnSigna Web - Backplane Application
Choose a stage of the DIMM system design process to locate tools and information for that phase.
Contents System architecture | Hardware specification | Simulation | Layout (Coming soon) | Prototype build | Validation/Testing
System architecture
VMEbus International Trade Association (VITA) (exiting Fairchild) PCI Industrial Computer Manufacturers Group (exiting Fairchild) Papers/articles/presentations Cost and Technology Challenges in the Design of Multi-Gigabit Interconnects: Some Thoughts and Observations Concerning Losses in FR-4. By Dr. Ed Sayre, President and CEO of North East Systems Associates, Inc. PDF (777 K) High-Performance Backplane Architectures Signal Integrity By Lee Sledjeski, Fairchild Semiconductor PDF (732 K) Natural Resonances in Multi-drop Backplane Structures. By The Staff of North East Systems Associates, Inc. PDF (786 K) Signal Integrity, Bandwidth and Backplane Termination. By Dr. Edward P. Sayre, P.E., and Dr. Jinhua Chen, North East Systems Associates, Inc. PDF (688 K)
Papers/articles/presentations Connection Systems, Signal Integrity Solutions for a High-Speed GTLP Backplane By Craig Klem, Fairchild Semiconductor and Michael Baxter, North East Systems Associates, Inc. PDF (726 K) Save the Black Magic for Connectors. . . Backplane Design Should be Straightforward! By Robert Cutler, Independent Consultant to Teradyne PDF (1,485 K)
GTLP Product Information GTLP Products Line Card PDF (493 K)
VME product information VME Products
Simulation
Timing and functionality simulation Timing domain analysis systems (exiting Fairchild) Free model foundry (exiting Fairchild) Signal integrity simulation IBIS models HSPICE models
Backplane Simulation EnSigna Backplane Simulator
Simulation support Use the EnSigna Lab Special request form for more information and assistance on specific design challenges.
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Prototype build
Request samples
Validation and testing
Validation and testing support Use the EnSigna Web Special request form for more information and assistance on specific design challenges.