EXAMPLE 7. GATE CHARGE TEST CIRCUIT
*==================================
.param vdd=1
.step param (vdd) 12 48 12 

Vd      3    0    DC    {vdd}
V_Id    2    5
Vg      1    2    DC    3.2
Ig      0    4    PULSE (0  1m  0u   10n   10n   300m    15)

X1      3    1    2    NDP7061l
X2      5    4    0    NDP7061l
.IC     V(4)=0    V(5)={vdd}

.LIB    c:\spicedis\dmos\ndp7061l.cir
.TRAN   10.0ns   100.0us   0n
.PROBE  V(4)        ; Vgs ( time axis in (us) = gate charge axis in (nC). ie Q=it )  
+       I(V_Id)     ; Id
+       V(5)        ; Vds
.OPTIONS    ITL4=40   ITL5=0    RELTOL=0.05   TNOM=25
.END