The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D-type input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.

All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

• Ideal buffer for microprocessor or memory
• Eight edge-triggered D-type flip-flops
• Buffered common clock
• Buffered, asynchronous master reset
• See 377 for clock enable version
• See 373 for transparent latch version
• See 374 for 3-STATE version
• Outputs source/sink 24 mA
• 74ACT273 has TTL-compatible inputs