The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the bus output is in the high impedance state.

The LVTH573 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These octal latches are designed for low-voltage (3.3V) V_CC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT573 and LVTH573 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.

• Input and output interface capability to systems at 5V V_CC
• Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH573), also available without bushold feature (74LVT573)
• Live insertion/extraction permitted
• Power Up/Down high impedance provides glitch-free bus loading
• Outputs source/sink -32 mA/+64 mA
• Functionally compatible with the 74 series 573
• Latch-up performance exceeds 500 mA
• ESD performance:

  Human-body model > 2000V

  Machine model > 200V

  Charged-device model > 1000V