74LVTH162373

The LVTH162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the outputs are in a high impedance state.     The LVTH162373 is designed with equivalent 25ohm series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.     The LVTH162373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.     These latches are designed for low-voltage (3.3V) V_CC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH162373 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.

• Fairchild 1,000 piece Budgetary Pricing. *
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Product	Product Status	Eco Status	*Pricing	Package Type	Leads	Packing Method	Package Drawing	**Package Marking Convention	Qualification Support	RoHS IPC1752	RoHS/REACH/ JIG Certificate of Compliance
74LVTH162373MTD	Full Production	Green as of May 2012	$1	TSSOP 48L	48	RAIL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:LVTH162373	FIT :  1.1   ESD (CDM) :  1000  V ESD (HBM) :  2000  V Show more ... Moisture Sensitivity Level (MSL) :  2   Max Reflow Temp :  260
74LVTH162373MTX	Full Production	Green as of May 2012	$0.9	TSSOP 48L	48	TAPE REEL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:LVTH162373	FIT :  1.1   ESD (CDM) :  1000  V ESD (HBM) :  2000  V Show more ... Moisture Sensitivity Level (MSL) :  2   Max Reflow Temp :  260