74LVX273

The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously.     The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.     All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.

• Fairchild 1,000 piece Budgetary Pricing. *
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• Top mark packaging information for product 74LVX273 is available. **

Product	Product Status	Eco Status	*Pricing	Package Type	Leads	Packing Method	Package Drawing	**Package Marking Convention	RoHS IPC1752	RoHS/REACH/JIG Certificate of Compliance
74LVX273MTCX	Full Production	Green as of Aug 2011	$0.292	TSSOP	20	TAPE REEL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:LVX273
74LVX273MTC	Full Production	Green as of Aug 2011	$0.292	TSSOP	20	RAIL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:LVX273
74LVX273MX	Full Production	ROHS Compliant	$0.432	SOIC-Wide	20	TAPE REEL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:LVX273
74LVX273M	Full Production	ROHS Compliant	$0.432	SOIC-Wide	20	RAIL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:LVX273