The VCX162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB# and OEBA#), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB# and CLKENBA#) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-to-LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB# is active-LOW. When OEAB# is HIGH, the outputs are in the HIGH-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA#, LEBA, CLKBA and CLKENBA#.

The 74VCX162601 is designed for low voltage (1.4V to 3.6V) V_CC applications with I/O compatibility up to 3.6V. The VCX162601 is also designed with 26ohm series resistors in the B-Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

• 1.4V to 3.6V V_CC supply operation
• 3.6V tolerant inputs and outputs
• 26ohm series resistors in B-Port outputs
• t_PD (A to B)

  3.8 ns max for 3.0V to 3.6V V_CC

• Power-down high impedance inputs and outputs
• Supports live insertion/withdrawal (Note 1)
• Static Drive (I_OH/I_OL B outputs)

  ±12 mA @ 3.0V V_CC

• Uses patented noise/EMI reduction circuitry
• Latchup performance exceeds 300 mA
• ESD performance:

  Human body model > 2000V

  Machine model >200V