74VHC161284 − IEEE 161284 Transceiver

The VHC161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA). The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the V_CC supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard LOW-drive CMOS outputs. The DIR input controls data flow on the A₁-A₈/B₁-B₈ transceiver pins.

Download Datasheet Buy Products Request Free Samples

Product Status/Pricing/Packaging

Index	Product	Product & Eco Status	*Pricing	Packaging & Packing Info	**Package Marking Convention	Qualification Support	Compliance Certificates
0	74VHC161284MTDX	Full Production Green as of May 2012	$0.64	TSSOP 48L Details TSSOP 48L Drawing TAPE REEL	Line 1:$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K Line 2:VHC161284	FIT : 0.9 ESD (HBM) : 2000 V Moisture Sensitivity Level (MSL) : 2 Show more... Max Reflow Temp : 260	RoHS IPC1752 RoHS/REACH/JIG RoHS/REACH/JIG

Fairchild 1,000 piece Budgetary Pricing. *
If there is no sample button displayed at the top of the page, please contact one of the Fairchild distributors or your local sales office to obtain samples.
Top mark packaging information for product 74VHC161284 is available. **

Features

Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals
Replaces the function of two (2) 74ACT1284 devices
All inputs have hysteresis to provide noise margin
B and Y output resistance optimized to drive external cable
B and Y outputs in high impedance mode during power down
Inputs and outputs on cable side have internal pull-up resistors
Flow-through pin configuration allows easy interface between the Peripheral and Host

Applications

TBA

Application Notes

Application Note	Description
AN-5010	IEEE 1284 Interface Design Solutions(223 K) 05-Mar-2011

Additional Resources

Design Tools Knowledgebase – Ask a Question Find a local sales office Product change notices (PCN) How to Buy Products or Order Samples

Loading Feedback Form...


Thank you for providing us with feedback regarding the Fairchild website. Your feedback has been submitted to our web team and will be reviewed. You may be contacted in the event that we have follow-up questions about the feedback you have provided.

	If you have a product- or technical-support related issue, please use our Knowledge Base Support Request Form.
	If you have a comment or suggestion about our website, or want to report a website problem or error, please let us know in the form below. We require your contact information in case we have follow-up questions about the feedback you give us. We review all feedback submitted, but may not be able to respond back to all submissions.
	* Indicates required fields

			First Name *

			Email Address *

			Operating System

			Internet Connection Speed

	Last Name *

	Telephone Number

	Web Browser

	Type of Issue or Feedback

	Want to use your existing contact information from your My Fairchild account?
	Email Address

	Password

Please provide the link (exact URL) of the web page(s) for which you want to report an issue or provide feedback:

Do you want to be contacted by Fairchild? Yes No

Please describe the issue or feedback in as much details as possible (max 1000 characters):

Slide to enable Submit button:

Locked

Unlocked