The CD4724BC is an 8-bit addressable latch with three address inputs (A0-A2), an active low enable input (E#), active high clear input (C_L), a data input (D) and eight outputs (Q0-Q7).

Data is entered into a particular bit in the latch when that is addressed by the address inputs and the enable (E#) is LOW. Data entry is inhibited when enable (E#) is HIGH.

When clear (C_L) and enable (E#) are HIGH, all outputs are LOW. When clear (C_L) is HIGH and enable (E#) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E# = C_L = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E# = HIGH, C_L = LOW).

• Wide supply voltage range: 3.0V to 15V
• High noise immunity: 0.45 V_DD (typ.)
• Low power TTL compatibility:

  fan out of 2 driving 74L or 1 driving 74LS

• Serial to parallel capability
• Storage register capability
• Random (addressable) data entry
• Active high demultiplexing capability
• Common active high clear