This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. The 3-STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or ramp-down. This eliminates bus glitching problems that arise during power-up and power-down. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.

• Advanced low power oxide-isolated ion-implanted Schottky TTL process
• Functional and pin compatible with the 74LS counterpart
• Switching response specified into 500ohm and 50 pF load
• Switching response specifications guaranteed over full temperature and V_CC supply range
• PNP input design reduces input loading
• Low level drive current: 74ALS = 24 mA