This advanced low power Schottky device contains 8 pairs of 3-STATE logic elements configured as octal bus transceivers. These circuits are designed for use in memory, microprocessor systems and in asynchronous bidirectional data buses. Two way communication between buses is controlled by the (DIR) input. Data transmits either from the A bus to the B bus or from the B bus to the A bus. Both the driver and receiver outputs can be disabled via the (G#) enable input which causes outputs to enter the high impedance mode so that the buses are effectively isolated.

• Advanced oxide-isolated, ion-implanted Schottky TTL process
• Non-inverting logic output
• Glitch free bus during power up and down
• 3-STATE outputs independently controlled on A and B buses
• Low output impedance to drive terminated transmission lines to 133ohm
• Switching response specified into 500ohm/50 pF
• Specified to interface with CMOS at V_OH = V_CC - 2V
• PNP inputs to reduce input loading
• Switching specifications guaranteed over full temperature and V_CC range