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More DDR product information
The FAN5078 DDR memory regulator combines a high-efficiency Pulse-Width Modulated (PWM) controller to generate the memory supply voltage, VDDQ, and a linear regulator to generate termination voltage (VTT).
Synchronous rectification provides high efficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET’s RDS(ON) to sense current.
The VDDQ PWM regulator is a sampled, current-mode control with external compensation to achieve fast load-transient response and provide system design optimization.
The VTT regulator derives its reference and takes its power from the VDDQ PWM regulator output. The VTT termination regulator is capable of sourcing or sinking up to 1.5A peak currents.
In S5 M1 mode, the VDDQ switcher, VTT regulator, and the 3.3V regulators remain on. S3 mode keeps these regulators on and turns on an external P-channel to provide 5V USB.
A single soft-start capacitor enables controlled slew rates for both VDDQ and 3.3V-ALW outputs.
PGOOD becomes true in S0 only after all regulators have achieved stable outputs.
In S5 (EN = 0), the 3.3V internal LDO stays on while the other regulators are powered down.
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