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General Description
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These N & P-Channel logic level enhancement mode field effect
transistors are produced using Fairchild’s proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage applications
as a replacement for bipolar digital transistors and small
signal MOSFETs. Since bias resistors are not required, this dual
digital FET can replace several different digital transistors, with
different bias resistor values.
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Features
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Q1: N-Channel
Max rDS(on) = 0.4O at VGS = 4.5V, ID = 0.75A
Max rDS(on) = 0.5O at VGS = 2.7V, ID = 0.67A
Q2: P-Channel
Max rDS(on) = 1.1O at VGS = –4.5V, ID = –0.41A
Max rDS(on) = 1.5O at VGS = –2.7V, ID = –0.25A
Very low level gate drive requirements allowing direct
operation in 3V circuits(VGS(th) <1.5V)
Very small package outline SC70-6
RoHS Compliant
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Datasheet
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