FDV302P

Digital FET,P-Channel

General DescriptionGeneral Description

This P-Channel logic level enhancement mode field effect transistor is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series.

Product Status/Pricing/PackagingProduct Status/Pricing/Packaging

ProductProduct statusEco StatusPricing*Package typeLeadsPacking methodPackage DrawingPackage Marking Convention**
FDV302PFull ProductionRoHS Compliant$0.106SOT-233TAPE REEL PDFLine 1: &E&Y (Binary Calendar Year Coding)
Line 2: 302P

FeaturesFeatures


  • -25 V, -0.12 A continuous, -0.5 A Peak. RDS(ON) = 13 W @ VGS= -2.7 V, RDS(ON) = 10 W @ VGS = -4.5 V.
  • Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V.
  • Gate-Source Zener for ESD ruggedness. >6kV Human Body Model.
  • Compact industry standard SOT-23 surface mount package.
  • Replace many PNP digital transistors (DTCx and DCDx) with one DMOS FET.

ModelsModels

For additional information please visit the Models page.

Package & leadsConditionTemperature rangeSoftware versionRevision date
PSPICE
SOT-23-3Electrical25°C to 125°COrcad 9.1Oct 23, 2001

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