FIN1018

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3.3V LVDS 1-Bit High Speed Differential Receiver

General Description

This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data. The FIN1018 can be paired with its companion driver, the FIN1017, or with any other LVDS driver.

Product Status/Pricing/Packing

Fairchild 1,000 piece Budgetary Pricing. *
If there is no sample button displayed at the top of the page, please contact one of the Fairchild distributors or your local sales office to obtain samples.
Top mark packaging information for product FIN1018 is available. **

Product	Product Status	Eco Status	*Pricing	Package Type	Leads	Packing Method	Package Drawing	**Package Marking Convention	RoHS IPC1752	RoHS/REACH/JIG Certificate of Compliance
FIN1018K8X	Full Production	Green as of Aug 2006	$0.54	US8	8	TAPE REEL		Line 1:&2 (2-Digit Date Code) &K Line 2:1018 Line 3:$Y (Fairchild logo) &Z (Asm. Plant Code)
FIN1018MX	Full Production	Green as of Nov 2008	$0.51	SO-8	8	TAPE REEL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:FIN Line 3:1018

Support

Engineering Connections

Qualification Support

Customer qualification data for the FIN1018K8X
Customer qualification data for the FIN1018MX

Features

Greater than 400Mbs data rate
3.3V power supply operation
0.4ns maximum pulse skew
2.5ns maximum propagation delay
Low power dissipation
Power-Off protection
Fail safe protection for open-circuit, shorted and terminated conditions
Meets or exceeds the TIA/EIA-644 LVDS standard
Flow-through pinout simplifies PCB layout
8-Lead SOIC and US-8 packages save space

Applications

Media Tablets

Mobile Handsets

PMP/MP3 Players

Storage & Peripherals

Wireless LAN Card & Broadband Access

Application Notes

AN-5048: System Clock Distribution Example Using LVDS (63 K) Mar 03, 2011
AN-5029: Interfacing Between PECL and LVDS Differential Technologies (234 K) Mar 03, 2011
AN-5047: Live Insertion Using Low Voltage Differential Signaling (71 K) Mar 03, 2011

Browse All Application Notes

Models

For additional information please visit the Models page .

Package & leads	Condition	Temperature range	Vcc range	Software version	Revision date
HSPICE
US8-8	Slow	-40°C to 85°C	3V to 3.6V	99.4	Apr 26, 2011
	Typical	-40°C to 85°C	3V to 3.6V	99.4	Apr 26, 2011
	Fast	-40°C to 85°C	3V to 3.6V	99.4	Apr 26, 2011
IBIS
US8-8	All	-40°C to 85°C	3V to 3.6V	3.2	Apr 26, 2011