FIN1032

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3.3V LVDS 4-Bit High Speed Differential Receiver

General Description

This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1032 can be paired with its companion driver, the FIN1031, or any other Fairchild LVDS driver.

Product Status/Pricing/Packing

Fairchild 1,000 piece Budgetary Pricing. *
If there is no sample button displayed at the top of the page, please contact one of the Fairchild distributors or your local sales office to obtain samples.
Top mark packaging information for product FIN1032 is available. **

Product	Product Status	Eco Status	*Pricing	Package Type	Leads	Packing Method	Package Drawing	**Package Marking Convention	RoHS IPC1752	RoHS/REACH/JIG Certificate of Compliance
FIN1032MTCX	Full Production	Green as of Jul 2011	$1.06	TSSOP	16	TAPE REEL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:FIN1032
FIN1032MX	Full Production	ROHS Compliant	$1.06	SOIC	16	TAPE REEL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:FIN1032

Support

Engineering Connections

Qualification Support

Customer qualification data for the FIN1032MTCX
Customer qualification data for the FIN1032MX

Features

Greater than 400Mbs data rate
3.3V power supply operation
0.4ns maximum differential pulse skew
2.5ns maximum propagation delay
Low power dissipation
Power OFF protection
Fail safe protection for open-circuit, shorted and terminated conditions
Meets or exceeds the TIA/EIA-644 LVDS standard
Pin compatible with equivalent RS-422 and LVPECL devices
16-Lead SOIC and TSSOP packages save space

Applications

Media Tablets

Mobile Handsets

PMP/MP3 Players

Storage & Peripherals

Wireless LAN Card & Broadband Access

Application Notes

AN-5046: LVDS Receiver Failsafe Biasing Networks (77 K) Mar 03, 2011

Browse All Application Notes

Models

For additional information please visit the Models page .

Package & leads	Condition	Temperature range	Vcc range	Software version	Revision date
HSPICE
SOIC-16	Typical	-40°C to 85°C	3V to 3.6V	99.4	Apr 26, 2011
	Slow	-40°C to 85°C	3V to 3.6V	99.4	Apr 26, 2011
	Fast	-40°C to 85°C	3V to 3.6V	99.4	Apr 26, 2011
IBIS
SOIC-16	All	-40°C to 85°C	3V to 3.6V	3.2	Apr 26, 2011