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LVDS 21-Bit Serializers/De-Serializers
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General Description
The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low-Voltage
TTL) data into three serial LVDS (Low-Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit clock, 21 bits of
input LVTTL data are sampled and transmitted.
The FIN1218 and FIN1216 receive and convert the three serial LVDS data
streams back into 21 bits of LVTTL data. Table 1 provides a matrix summary of
the serializers and de-serializers available. For the FIN1217, at a transmit
clock frequency of 85MHz, 21 bits of LVTTL data are transmitted at a rate of
595Mbps per LVDS channel.
These chipsets solve EMI and cable size problems associated with wide and
high-speed TTL interfaces.
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Features
- Low Power Consumption
- 20MHz to 85MHz Shift Clock Support
- 50% Duty Cycle on the Clock Output of Receiver
- ±1V Common-mode Range ~1.2V
- Narrow Bus Reduces Cable Size and Cost
- High Throughput: 1.785Gbps
- Up to 595Mbps per Channel
- Internal PLL with No External Components
- Compatible with TIA/EIA-644 Specification
- Offered in 48-lead TSSOP Packages
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