|  |
Low Voltage 28-Bit Flat Panel Display Link Serializers
| | |  |  |  |
|
|
General Description
The FIN3385 and FIN3383 transform 28-bit wide parallel LVTTL (Low Voltage
TTL) data into 4 serial LVDS (Low-Voltage Differential Signaling) data streams.
A phase-locked transmit clock is transmitted in parallel with the data stream
over a separate LVDS link. Every cycle of transmit clock 28 bits of input LVTTL
data are sampled and transmitted.
The FIN3386 and FIN3384 receive and convert the 4/3 serial LVDS data streams
back into 28/21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the
serializers and deserializers available. For the FIN3385, at a transmit clock
frequency of 85MHz, 28-bits of LVTTL data are transmitted at a rate of 595Mbps
per LVDS channel. These chipsets solve EMI and cable size problems associated
with wide and high-speed TTL interfaces.
|
back to top
Features
- Low Power Consumption
- 20MHz to 85MHz Shift Clock Support
- ±1V Common-Mode Range around 1.2V
- Narrow Bus Reduces Cable Size and Cost
- High Throughput (up to 2.38Gbps)
- Internal PLL with No External Component
- Compatible with TIA/EIA-644 Specification
- 56-Lead TSSOP Package
| | |