The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control which minimizes signal settling times. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V and the receiver threshold is 1.0V.

• Bidirectional interface between GTLP and TTL logic levels
• Designed with an edge rate control circuit to reduce output noise on GTLP port
• V_REF pin provides external supply reference voltage for receiver threshold adjustability
• Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
• TTL compatible Driver and Control inputs
• Designed using Fairchild advanced CMOS technology
• Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
• Power up/down and power off high impedance for live insertion
• 5V tolerant inputs and outputs on LVTTL port
• Open drain on GTLP to support wired-or connection
• Flow-through pinout optimizes PCB layout
• D-type flip-flop, latch and transparent data paths
• A Port outputs source/sink -32 mA/+32 mA