GTLP16612

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CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

General Description

The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (1V), reduced input threshold levels and output edge rate control which minimizes signal settling times. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V and the receiver threshold is 1.0V.

Product Status/Pricing/Packing

Fairchild 1,000 piece Budgetary Pricing. *
If there is no sample button displayed at the top of the page, please contact one of the Fairchild distributors or your local sales office to obtain samples.
Top mark packaging information for product GTLP16612 is available. **

Product	Product Status	Eco Status	*Pricing	Package Type	Leads	Packing Method	Package Drawing	**Package Marking Convention	RoHS IPC1752	RoHS/REACH/JIG Certificate of Compliance
GTLP16612MTD	Full Production	ROHS Compliant	$7.16	TSSOP	56	RAIL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:GTLP16612
GTLP16612MTDX	Full Production	ROHS Compliant	$7.16	TSSOP	56	TAPE REEL		Line 1:$Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2:GTLP16612

Customer qualification data for the GTLP16612MTD
Customer qualification data for the GTLP16612MTDX

Features

Bidirectional interface between GTLP and TTL logic levels
Designed with an edge rate control circuit to reduce output noise on GTLP port
V_REF pin provides external supply reference voltage for receiver threshold adjustability
Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
TTL compatible Driver and Control inputs
Designed using Fairchild advanced CMOS technology
Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
Power up/down and power off high impedance for live insertion
5V tolerant inputs and outputs on LVTTL port
Open drain on GTLP to support wired-or connection
Flow-through pinout optimizes PCB layout
D-type flip-flop, latch and transparent data paths
A Port outputs source/sink -32 mA/+32 mA

Applications

Automation

Broadband Access

Broadband Modem

Broadcast & Studio

Building & Home Control

Camcorder

Central Office

Consumer Appliances

CRT/RPTV

Desktop PC

DSC

DVD

E-book Reader

Enterprise Voice Network

Graphic Card

Home Audio System Components

LCD Monitor

LCD TV

Long-haul & Metro

Media Tablets

Medical Electronics/Devices

Mobile Comm Infrastructure

Mobile Handsets

Notebook PC

Other Audio & Video

Other Consumer Electronics

Other Data Processing

Other Industrial

Other Wired Communications

Other Wireless Communications

PC Server

PDP TV

PMP/MP3 Players

Printer

Routers & LAN Switches

SAN

Server & Mainframe

Set Top Boxes

Storage & Peripherals

Test and Measurement

Video Game Console

Wireless LAN Access Point/Router

Wireless LAN Card & Broadband Access

Workstation

Application Notes

AN-600: Understanding Latch-up in Advanced CMOS Logic (54 K) Mar 05, 2011
MS-549: Fairchild Switch Product Feature Matrix (15 K) Mar 05, 2011
MS-565: Backplane Designer's Guide - Section 5 - Backplane Signal Conditioning (267 K) Mar 05, 2011
AN-1072: GTLP Output Control Circuitry: Reduces Noise and Enhances System Performance (81 K) Mar 05, 2011
MS-548: GTLP AC Loading Circuits and Waveforms (28 K) Mar 05, 2011
AN-5025: Applications Using the GTLP10B320 (387 K) Mar 05, 2011
AN-363: Designing with TTL (32 K) Mar 05, 2011
AN-1072J: GTLP Output Control Circuitry: Reduces Noise and Enhances System Performance (Japanese Translation) (426 K) Mar 05, 2011
AN-5013: GTLP in BTL Applications (56 K) Mar 05, 2011
AN-368: An Introduction to and Comparison of 74HCT TTL Compatible CMOS Logic (85 K) Mar 05, 2011
MS-507: Extended Characterization Data for GTLP16612, GTLP16616, GTLP16617 (46 K) Mar 05, 2011
MS-537: Interface Products Ordering Information and Physical Dimensions (596 K) Mar 05, 2011
AN-5031: GTLP Power Configuration (1,206 K) Mar 05, 2011
AN-1065SC: GTLP: An Interface Technology for Bus and Backplane Applications (Chinese Translation) (289 K) Mar 05, 2011
AN-1097: GTLP: Understanding Output Drive (45 K) Mar 05, 2011
MS-550: GTLP Product Feature Matrix (19 K) Mar 05, 2011
AN-1070SC: Fairchild's GTLP vs. TI's GTL: A Performance Comparison from a Systems Perspective (Chinese Translation) (610 K) Mar 05, 2011
AN-5002: GTLP: Single vs. Multiple Output Switching Technical Discussion (39 K) Mar 05, 2011
MS-506: Extended Characterization Data for GTLP6C816 (87 K) Mar 05, 2011
MS-533: GTLP Extended Characterization Data - Description of Parameters (14 K) Mar 05, 2011
AN-1065K: GTLP: An Interface Technology for Bus and Backplane Applications (Korean Translation) (235 K) Mar 05, 2011
AN-375: High-Speed-CMOS Designs Address Noise and I/O Levels (238 K) Mar 05, 2011
MS-508: Extended Characterization Data for GTLP8T306 (40 K) Mar 05, 2011
AN-1070K: Fairchild's GTLP vs. TI's GTL: A Performance Comparison from a System Perspective (Korean Translation) (538 K) Mar 05, 2011
MS-532: GTLP Description and Family Characteristics (204 K) Mar 05, 2011
AN-1065J: GTLP: An Interface Technology for Bus and Backplane Applications (Japanese Translation) (339 K) Mar 05, 2011
AN-1070: GTLP vs. GTL: A Performance Comparison from a System Perspective (111 K) Mar 05, 2011
AN-1097SC: GTLP: Understanding Output Drive (Chinese Translation) (284 K) Mar 05, 2011
AN-1065: GTLP: An Interface Technology for Bus and Backplane Applications (95 K) Mar 05, 2011
AN-1097K: GTLP: Understanding Output Drive (Korean Translation) (233 K) Mar 05, 2011
AN-1097J: GTLP: Understanding Output Drive (Japanese Translation) (336 K) Mar 05, 2011

Browse All Application Notes

Models

For additional information please visit the Models page .

Package & leads	Condition	Temperature range	Vcc range	Software version	Revision date
IBIS
TSSOP-56	All	-40°C to 85°C	3V to 3.6V	2.1	Apr 26, 2011
HSPICE
TSSOP-56	Typical	-40°C to 85°C	3.15V to 3.45V	97.1	Apr 26, 2011
	Slow	-40°C to 85°C	3.15V to 3.45V	97.1	Apr 26, 2011
	Fast	-40°C to 85°C	3.15V to 3.45V	97.1	Apr 26, 2011