GTLP18T612

18-Bit LVTTL/GTLP Universal Bus Transceiver

General Description

The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V.

Product Status/Pricing/Packaging

Top mark packaging information for product GTLP18T612 is available.

Product	Product status	Eco Status	Package type	Leads	Packing method	Package Marking Convention**
GTLP18T612MEA	Lifetime Buy	Green	SSOP	56	RAIL	Line 1: $Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP18T612
GTLP18T612MEAX	Lifetime Buy	Green	SSOP	56	TAPE REEL	Line 1: $Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP18T612
GTLP18T612MTD	Lifetime Buy	RoHS Compliant	TSSOP	56	RAIL	Line 1: $Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP18T612
GTLP18T612MTDX	Lifetime Buy	RoHS Compliant	TSSOP	56	TAPE REEL	Line 1: $Y (Fairchild logo) &Z (Asm. Plant Code) &2 (2-Digit Date Code) &K Line 2: GTLP18T612

Customer qualification report for the GTLP18T612MEA
Customer qualification report for the GTLP18T612MEAX
Customer qualification report for the GTLP18T612MTD
Customer qualification report for the GTLP18T612MTDX

Features

Bidirectional interface between GTLP and LVTTL logic levels
Designed with edge rate control circuitry to reduce output noise on the GTLP port
V_REF pin provides external supply reference voltage for receiver threshold adjustibility
Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
TTL compatible driver and control inputs
Designed using Fairchild advanced BiCMOS technology
Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
Power up/down and power off high impedance for live insertion
Open drain on GTLP to support wired-or connection
Flow through pinout optimizes PCB layout
D-type flip-flop, latch and transparent data paths
A Port source/sink -24mA/+24mA
B Port sink +50mA
Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

Application Notes

MS-535: Extended Characterization Data GTLP18T612 (90 K) Mar 05, 2010
MS-548: GTLP AC Loading Circuits and Waveforms (27 K) Mar 05, 2010
MS-550: GTLP Product Feature Matrix (18 K) Mar 05, 2010

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Models

For additional information please visit the Models page.

Package & leads	Condition	Temperature range	Vcc range	Software version	Revision date
HSPICE
SSOP-56	Fast	-40°C to 85°C	3.15V to 3.45V	99.4	Feb 23, 2001
	Typical	-40°C to 85°C	3.15V to 3.45V	99.4	Feb 23, 2001
	Slow	-40°C to 85°C	3.15V to 3.45V	99.4	Feb 23, 2001
TSSOP-56	Fast	-40°C to 85°C	3.15V to 3.45V	99.4	Feb 23, 2001
	Typical	-40°C to 85°C	3.15V to 3.45V	99.4	Feb 23, 2001
	Slow	-40°C to 85°C	3.15V to 3.45V	99.4	Feb 23, 2001
IBIS
SSOP-56	All	-40°C to 85°C	3.15V to 3.45V	3.2	Dec 1, 2000
TSSOP-56	All	-40°C to 85°C	3.15V to 3.45V	3.2	Dec 1, 2000

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GTLP18T612

18-Bit LVTTL/GTLP Universal Bus Transceiver

General Description

Product Status/Pricing/Packaging

Support

Engineering Connections

Qualification Support

Features

Application Notes

Models

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