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GTLP18T612

18-Bit LVTTL/GTLP Universal Bus Transceiver

General DescriptionGeneral Description

The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V.

Product Status/Pricing/PackagingProduct Status/Pricing/Packaging

ProductProduct statusEco StatusPackage typeLeadsPacking methodPackage DrawingPackage Marking Convention**
GTLP18T612MEALifetime BuyGreenSSOP56RAIL PDFLine 1: $Y (Fairchild logo)
&Z (Asm. Plant Code)
&2 (2-Digit Date Code)
&K Line 2: GTLP18T612
GTLP18T612MEAXLifetime BuyGreenSSOP56TAPE REEL PDFLine 1: $Y (Fairchild logo)
&Z (Asm. Plant Code)
&2 (2-Digit Date Code)
&K Line 2: GTLP18T612
GTLP18T612MTDLifetime BuyRoHS CompliantTSSOP56RAIL PDFLine 1: $Y (Fairchild logo)
&Z (Asm. Plant Code)
&2 (2-Digit Date Code)
&K Line 2: GTLP18T612
GTLP18T612MTDXLifetime BuyRoHS CompliantTSSOP56TAPE REEL PDFLine 1: $Y (Fairchild logo)
&Z (Asm. Plant Code)
&2 (2-Digit Date Code)
&K Line 2: GTLP18T612

FeaturesFeatures


  • Bidirectional interface between GTLP and LVTTL logic levels
  • Designed with edge rate control circuitry to reduce output noise on the GTLP port
  • VREF pin provides external supply reference voltage for receiver threshold adjustibility
  • Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
  • TTL compatible driver and control inputs
  • Designed using Fairchild advanced BiCMOS technology
  • Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
  • Power up/down and power off high impedance for live insertion
  • Open drain on GTLP to support wired-or connection
  • Flow through pinout optimizes PCB layout
  • D-type flip-flop, latch and transparent data paths
  • A Port source/sink -24mA/+24mA
  • B Port sink +50mA
  • Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

Application NotesApplication Notes

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ModelsModels

For additional information please visit the Models page.

Package & leadsConditionTemperature rangeVcc rangeSoftware versionRevision date
HSPICE
SSOP-56Slow-40°C to 85°C3.15V to 3.45V99.4Feb 23, 2001
Typical-40°C to 85°C3.15V to 3.45V99.4Feb 23, 2001
Fast-40°C to 85°C3.15V to 3.45V99.4Feb 23, 2001
TSSOP-56Typical-40°C to 85°C3.15V to 3.45V99.4Feb 23, 2001
Fast-40°C to 85°C3.15V to 3.45V99.4Feb 23, 2001
Slow-40°C to 85°C3.15V to 3.45V99.4Feb 23, 2001
IBIS
SSOP-56All-40°C to 85°C3.15V to 3.45V3.2Dec 1, 2000
TSSOP-56All-40°C to 85°C3.15V to 3.45V3.2Dec 1, 2000

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