The GTLP2T152 is a 2-bit transceiver that provides LVTTL-to-GTLP signal level translation. Data directional control is handled with a transmit/receive pin. High-speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus-settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP has internal edge-rate control and is process, voltage and temperature compensated. GTLP's I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are: V_OL = 0.5V, V_OH = 1.5V, and V_REF = 1V.

• Bidirectional interface between GTLP and LVTTL logic levels
• Designed with edge rate control circuitry to reduce output noise on the GTLP port
• V_REF pin provides external supply reference voltage for receiver threshold adjustibility
• Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
• TTL compatible driver and control inputs
• Designed using Fairchild advanced BiCMOS technology
• Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
• Power up/down and power off high impedance for live insertion
• Open drain on GTLP to support wired-or connection
• Flow through pinout optimizes PCB layout
• A Port source/sink -24mA/+24mA
• B Port sink +50mA