The GTLP6C817 is a low drive clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the GunningTransceiver logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.

• Interface between LVTTL and GTLP logic levels
• Designed with edge rate control circuitry to reduce output noise on the GTLP port
• V_REF pin provides external supply reference voltage for receiver threshold adjustibility
• Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
• TTL compatible driver and control inputs
• Designed using Fairchild advanced CMOS technology
• Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
• Power up/down and power off high impedance for live insertion
• 5V over voltage tolerance on LVTTL ports
• Open drain on GTLP to support wired-or connection
• A Port source/sink -12mA/+12mA
• B Port sink +40mA
• 1:6 fanout clock driver for TTL port
• 1:2 fanout clock driver for GTLP port