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P-Channel Logic Level Enhancement Mode Field Effect Transistor
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General Description
These logic level P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
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Features
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-24 A, -20 V. RDS(ON) = 0.05 W @ VGS= -4.5 V, RDS(ON) = 0.07 W @ VGS= -2.7 V, RDS(ON) = 0.075 W @ VGS= -2.5 V.
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Critical DC electrical parameters specified at elevated temperature.
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Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor.
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175°C maximum junction temperature rating.
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High density cell design for extremely low RDS(ON).
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TO-220 and TO-263 (D2PAK) package for both through hole and surface mount applications.
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