The ALVC16841 contains twenty non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the outputs are in a high impedance state.

The 74ALVC16841 is designed for low voltage (1.65V to 3.6V) V_CC applications with I/O compatibility up to 3.6V.

The 74ALVC16841 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.

• 1.65V-3.6V V_CC supply operation
• 3.6V tolerant inputs and outputs
• t_PD (D_n to O_n)

  3.5 ns max for 3.0V to 3.6V V_CC

  3.9 ns max for 2.3V to 2.7V V_CC

  6.8 ns max for 1.65V to 1.95V V_CC

• Power-off high impedance inputs and outputs
• Supports live insertion and withdrawal (Note 1)
• Uses patented noise/EMI reduction circuitry
• Latchup conforms to JEDEC JED78
• ESD performance:

  Human body model > 2000V

  Machine model > 200V