The VCX16601 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB# and OEBA#), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB# and CLKENBA#) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-to-LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB# is LOW, the outputs are active. When OEAB# is HIGH, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA#, LEBA, CLKBA and CLKENBA#.

The VCX16601 is designed for low voltage (1.4V to 3.6V) V_CC applications with I/O capability up to 3.6V.

The VCX16601 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.

• 1.4V to 3.6V V_CC supply operation
• 3.6V tolerant inputs and outputs
• t_PD (A to B, B to A)

  2.9 ns max for 3.0V to 3.6V V_CC

• Power-down high impedance inputs and outputs
• Supports live insertion/withdrawal (Note 1)
• Static Drive (I_OH/I_OL)

  ±24 mA @ 3.0V V_CC

• Uses patented noise/EMI reduction circuitry
• Latchup performance exceeds 300 mA
• ESD performance:

  Human body model > 2000V

  Machine model >200V

• Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)