Fairchild Semiconductor
FIN1018
3.3V LVDS 1-Bit High Speed Differential Receiver

General Description

This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data.

The FIN1018 can be paired with its companion driver, the FIN1017, or with any other LVDS driver.

Features

  • Greater than 400Mbs data rate
  • 3.3V power supply operation
  • 0.4ns maximum pulse skew
  • 2.5ns maximum propagation delay
  • Low power dissipation
  • Power-Off protection
  • Fail safe protection for open-circuit, shorted and terminated conditions
  • Meets or exceeds the TIA/EIA-644 LVDS standard
  • Flow-through pinout simplifies PCB layout
  • 8-Lead SOIC and US-8 packages save space

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Product Status/Pricing/Packaging      buy now

ProductProduct statusEco StatusPricing*Package typeLeadsPacking methodPackage DrawingPackage Marking Convention**
FIN1018K8XFull ProductionGreen$0.53US88TAPE REEL PDFLine 1: &2 (2-Digit Date Code)
&K Line 2: 1018 Line 3: $Y&Z
FIN1018MFull ProductionGreen$0.50SOIC8RAIL PDFLine 1: $Y (Fairchild logo)
&Z (Asm. Plant Code)
&2 (2-Digit Date Code)
&K Line 2: FIN Line 3: 1018
FIN1018MXFull ProductionGreen$0.50SOIC8TAPE REEL PDFLine 1: $Y (Fairchild logo)
&Z (Asm. Plant Code)
&2 (2-Digit Date Code)
&K Line 2: FIN Line 3: 1018
* Fairchild 1,000 piece Budgetary Pricing
** A sample button will appear if the part is available through Fairchild's on-line samples program. If there is no sample button, please contact a Fairchild distributor to obtain samples

Package marking information for product FIN1018 is available. Click here for more information .

Models

Package & leadsConditionTemperature rangeVcc rangeSoftware versionRevision date
HSPICE
SOIC-8Slow-40°C to 85°C3V to 3.6V99.4Feb 12, 2001
Typical-40°C to 85°C3V to 3.6V99.4Feb 12, 2001
Fast-40°C to 85°C3V to 3.6V99.4Feb 12, 2001
US8-8Fast-40°C to 85°C3V to 3.6V99.4Feb 12, 2001
Slow-40°C to 85°C3V to 3.6V99.4Feb 12, 2001
Typical-40°C to 85°C3V to 3.6V99.4Feb 12, 2001
IBIS
SOIC-8All-40°C to 85°C3V to 3.6V3.2Jul 1, 2001
US8-8All-40°C to 85°C3V to 3.6V3.2Jul 1, 2001

Application Notes

AN-5029: Interfacing Between PECL and LVDS Differential Technologies (228 K) Nov 14, 2008
AN-5047: Live Insertion Using Low Voltage Differential Signaling (68 K) Nov 14, 2008
AN-5048: System Clock Distribution Example Using LVDS (61 K) Nov 14, 2008
 


Qualification Support

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Product
FIN1018K8X
FIN1018M
FIN1018MX


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