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FLMP Features & Benefits
Features
- Wireless construction reduces RDS(ON) contribution
- Reduced thermal resistance, JC & JA
- Excellent die size to PCB footprint ratio
- Low RDS(ON)
Benefits
- A “wireless”, source terminal die attach technique reduces the package resistance contribution by 75%
- Compared to many small outline packages where the die is fully encapsulated with high thermal impedance mold compound, the SSOT-6 FLMP provides a much lower thermal impedance path from the PCB to the MOSFET junction. This permits either better efficiency for the same current or a higher current density solution without sacrificing efficiency.
- The mechanical construction technique used in the assembly of the SSOT-6 FLMP allows a larger die size to be accommodated compared to the regular SSOT-6 package. This allows the same PCB area to accommodate a larger MOSFET die than previously possible, again providing more efficient solutions.
- Extremely low RDS(on) ratings in a package occupying less than 9mm2 of PCB area. The common SO-8 package occupies 30mm2
