Technology Data

RELIABILITY QUALIFICATION OF
POWER PRODUCTS

• Technology
• Failure Mechanisms
• Process Changes
• Sample Sizes
• Stress Test Definitions
• Stress Conditions
• Appendix A - Definitions

SCOPE

This document defines the procedure for the Reliability Qualification of Intersil Power Devices for new designs and major process changes.

The procedures established in this document are applicable to all newly designed products and products undergoing major process changes which are currently included in or will be added to the Intersil Power Device Catalog.

ADMINISTRATION

The administration of the program is the responsibility of the Quality and Reliability Manager at the Mountaintop location . The Mountaintop location has the responsibility for maintenance of all records pertaining to this program.

QUALIFICATION CATEGORIES

NEW DIE DESIGN

A die whose fabrication process utilizes unique steps, methods or techniques not supported by prior reliability data.

EXTENSION OF EXISTING DESIGN

A minor modification of an existing die design intended to extend its ratings.

NEW PACKAGE

A package not previously used by Intersil for power devices.

PRODUCT CATEGORIZATION

TECHNOLOGY

The following major categories of product referred to as "Technologies" have been defined as:

1. Bipolar Transistors
2. Surgector Protection Devices
3. High Speed Rectifiers
4. Power MOS transistors
5. Insulated Gate Bipolar Transistors (IGBT)
6. Mos Controlled Thyristor (MCT)

PROCESS

Each Technology may be further subdivided according to the specific process used to produce certain unique characteristics. As of the date of the latest revision of this document, the following process subsets are defined for each category.

BIPOLAR TRANSISTORS

1. Discrete NPN transistors
2. Discrete PNP transistors
3. Darlington NPN Transistors
4. Darlington PNP Transistors
5. SURGECTOR

HIGH SPEED RECTIFIER

• Low Voltage (<= 200 volts)
• High Voltage (> 200 volts)

POWER MOS TRANSISTOR

• High voltage (> 200 volts) Standard Gate
• Low voltage (<=200 volts) Standard Gate
• Low Voltage Logic Level Gate P-Channel
• Low Voltage Logic Level Gate N-Channel
• N-Channel High Cell Density (Megafet) Standard Gate
• P-Channel High Cell Density (Megafet) Standard Gate
• N-Channel High Cell Density (Megafet) Logic Level Gate
• P-Channel High Cell Density (Megafet) Logic Level Gate
• Current Limit Power MOS

INSULATED GATE BIPOLAR TRANSISTOR (IGBT)

• Standard IGBT (<=600 volts)
• Standard IGBT (> 600 volts)
• Ignition IGBT

MOS CONTROLLED THYRISTOR(MCT)

• MCT (<=600 volts)
• MCT (> 600 volts)

 

PROCEDURE FOR NEW DESIGNS

CONSTRUCTION ANALYSIS

The Design Engineering or Manufacturing Engineering activity shall provide an analysis of the process and construction details of each new design. Such details as geometry, metallization, oxide thickness, cell density, passivation, metal thickness, packaging, and any other pertinent information required shall be provided to allow the preparation of a comprehensive test plan.

QUALIFICATION CATEGORY ASSIGNMENT

Each new design proposal shall be evaluated by the Reliability Engineering activity and assigned to one of the Qualification Categories defined in IV.

PRODUCT CATEGORY ASSIGNMENT

The new design shall be assigned to one of the existing Technology/Process categories defined in V. In the event that none of the existing categories are applicable, the required new category/process shall be added to this document.

PREPARATION OF TEST PLAN

STRESS SELECTION

The primary criteria for the selection of stresses to be applied in the qualification process is provided in table 1. Each failure mode has identified one or more stress tests which may be chosen as a detector . It is recognized that these may be desi gn/process related as well as Applications related.

PREVIOUSLY ESTABLISHED PLANS

The test Matrices defined in item VIII of this document are recommended as guidelines for the stress selection process. This matrix has demonstrated a high degree of effectiveness in eliminating customer and field problems.

FMEA

Since table 1 is not exhaustive, a Design and/or Applications type FMEA should be conducted to insure that all potential failure modes and stresses which a new design may encounter have been identified.

TABLE 1
POWER DEVICE FAILURE MODES
MODE	STRESS
WIRE BOND LIFT	POWER CYCLING
DIE ATTACH DEGRADATION	POWER CYCLING TEMPERATURE CYCLING
DIE FRACTURE	>THERMAL SHOCK TEMPERATURE CYCLE
PACKAGE INTEGRITY	THERMAL SHOCK AUTOCLAVE HUMIDITY BIAS LEAD INTEGRITY SOLDER IMMERSION FLAMMABILITY HIGH POT
PASSIVATION INTEGRITY	THERMAL SHOCK HUMIDITY BIAS AUTOCLAVE HTRB
MOBILE IONICS	HTRB STORAGE LIFE OPERATING LIFE
PARAMETRIC DEGRADATION	SUBSTANTIALLY SAME AS MOBILE IONICS
CONTAMINATION RELATED	SUBSTANTIALLY SAME AS MOBILE IONICS

DESIGN REVIEW/KICKOFF MEETING

At the initiation of a new design, a meeting is conducted to review the new design proposal. At this meeting, the Quality and Reliability Manager, or his designated representative, will present a test plan for the qualification of the proposed product.

PREPARATION OF SAMPLES

The Product Design makes the necessary arrangements for the fabrication of the required samples within the framework of the following guidelines.

DESIGN VERIFICATION

Samples for design verification may be fabricated at any location. The outcome of the evaluation of the design verification samples will have no effect on the eventual reliability acceptance of the design. For the purposes of Design Verification of new die designs, it will not be necessary to use the package in which the product will eventually be qualified.

RELIABILITY ACCEPTANCE

Samples for Reliability Acceptance will be fabricated at the intended assembly location. The package will be the intended package of the design. All requirements of the final design will be met during the preparation of the acceptance samples.

SAMPLE GROUP "A" TESTING

Group "A" testing on the samples for reliability acceptance will be tested at the intended manufacturing location and will be tested in accordance with an official preliminary electrical specification. Only those tests appearing on the official electrical or preliminary electrical specification are allowed. The limits used must be the authorized factory limits with no special pad or safety margins allowed.

SAMPLE DELIVERY

It shall be the responsibility of the design activity to deliver the samples to the cognizant Reliability Engineer for testing and evaluation.

RELIABILITY TESTING

The Reliability activity shall subject the samples to the stress tests outlined in the previously accepted Test Plan. The cognizant Reliability Engineer shall issue such reports as may be required from time to time to keep the organization informed on the status of the acceptance testing. The final report shall be issued upon successful completion of the acceptance testing . This report shall become part of the documentation of the Factory Transfer Process. The Reliability group at the assembly location shall be responsible for the inclusion of the new design in Matrix I and II programs, after notification of the reliability approval.

PROCEDURE FOR PACKAGE QUALIFICATION

DESIGN REVIEW

A design review will be initiated by the package engineering activity to include manufacturing ,design, and reliability engineering.

CHOICE OF QUALIFICATION VEHICLE

The reliability activity will select a matrix of die sizes and voltage ranges consistent with the intended range of application of the package.

PACKAGE STRESS TESTS

The test plan will include appropriate tests from the matrix in item IX.C. The package related tests are annotated with the superscript letters "PQ".

REQUIREMENTS FOR ACCEPTANCE

The requirements for acceptance are those of new die design extended over the entire range of vehicles chosen in VII.B

PROCEDURE MAJOR CHANGES

Major changes as related to power device processing are defined in 999004. The procedure for major changes is similar to that defined for new design and new packages with the following exceptions: The design review meeting may be eliminated. The choice of stress tests is governed by table 1. and the type of changes

REQUIREMENTS FOR RELIABILITY ACCEPTANCE

NUMBER OF LOTS

The number of lots required for acceptance of a new design, or new package is a minimum of three. Where these involve more than one die, the lots should include the extremes of the design in voltage and size wherever possible. Major changes generally require three lots unless modified by conditions of Class Action. Extensions may be accepted with one lot or qualified by the process of class action.

LOT DEFINITION

A lot is defined as a continuous assembly run of 1000 pieces for the purposes of this document, except where product costs are high.

SAMPLE SIZES

The sample sizes submitted to the various stresses of the accepted test plan shall be as follows:

STRESS	SS	CUM. SS	LTPD	CUM LTPD
Power cyclingPQ	40	120	2	5
Operating Life	40	120	2	5
HTRB	40	120	2	5
HTGB	40	120	2	5
Storage Life	40	120	2	5
Temperature CyclePQ	40	120	2	5
Thermal ShockPQ	40	120	2	5
AutoclavePQ	25	75	4(1)	10
Relative Humidity Bias	40	120	2	5
Lead FatiguePQ	5	15	0	15
Lead BendPQ	5	15	0	15
Lead TorquePQ	5	15	0	15
Solder ImmersionPQ	77	231	3(2)0	1
FlammabilityPQ	2	6	0
FlammabilityPQ	2	6	0
Isolation ResistancePQ	77	231	0	1
VibrationPQ	8	24	1	15
Drop ShockPQ	8	24	1	15
Notes: PQ = Package Qualification Stress 1 = No opens due to corrosion 2 = No cracked die or packages

OVERALL LTPD REQUIRED FOR ACCEPTANCE

The overall LTPD will be approximately equal to 1. The accept number will correspond to the sample size rounded up to the nearest whole accept number.

ALLOWABLE MAXIMUM FAILURE RATE

The allowable maximum failure rate based on the individual stress sample sizes required by LTPD=5 and the required test times published in the following tables is 2.583% per 1000 hours. This estimate is based on the CHI SQUARE distribution using d.f. = 2c + 2, and 60% confidence. For methods of calculating the failure rate, see the appropriate entry in Appendix "B".

ADJUSTMENTS TO REQUIRED TEST TIME

Under the conditions that a test results in an accept number one greater than the maximum allowed, the test time may be extended to demonstrate an equivalent failure rate. This calculation is made by substituting the new accept number into the usual CHI SQUARE formula and working backward to obtain the total number of device hours required to demonstrate the failure rate. This adjustment is permissible for a maximum of one stress. For methods of calculating the adjustments see the appropriate entry in Appendix "B".

ACCEPTANCE BY CLASS ACTION

The three lot requirement may be adjusted or eliminated with the approval of the Manager of Reliability in certain special circumstances including but not limited to: High degree of similarity in products submitted as a group such as three different voltage categories of a product fabricated with the same mask set The addition of a new product with a high degree of similarity to a previously qualified product or group of products as in the case of product extensions. The latter stages of a program when sufficient data have been generated.

MODIFICATIONS TO TEST MATRIX

In certain special cases where the existence of sufficient compatible data can be documented, the test matrix may be amended. In these cases, RA.a1 form, which provides justification for the amended test plan, must be completed and approved by the Manager of Reliability. The justification must include the source of the data, a summary of the data, and the reasoning relative to its applicability . The form RA.a1 must be retained with the official qualification record maintained in the Reliability Assurance Test Area for the device.

DATA FORMAT

Variables data for end point readings will be taken wherever possible and recorded. When output on electronic media, it is retained in the reliability area in active electronic media until completion of the qualification acceptance. At a point in time governed by the availability of storage space, the data will be archived to permanent inactive magnetic media. Attribute data will be stored in a data base maintained in the reliability engineering area. Statistical summaries of parametric shifts should be made available to internal and external customers upon request.

NOTIFICATION OF ACCEPTANCE

Upon successful completion of acceptance testing, the cognizant Reliability Engineer will make notification to the Quality and Reliability Manager. and the responsible Engineering Manager. The notification will include all relevant data and failure analysis as well as a statement of the basis for the acceptance of the design.

CONTROL OF NON-ACCEPTED PRODUCT

Non-accepted products may not be shipped to customers other than in sample quantities of 50 pcs or less. Products shipped as samples must be branded with the appropriate disclaimer indicating that the product is not reliability accepted. All new families are placed on Hold until such time as approval is made by the cognizant reliability organization in the ECN/BOM system.

STRESS DEFINITIONS

POWER CYCLING (100)

Temperature cycling of the device under test by the alternate application of power and forced air cooling. The parameters specified are case temperature delta, the power developed, the duration of the test, and the number of cycles to each down period.

OPERATING LIFE (200)

The application of power to the main device junction with the intention of elevating the temperature. The parameters specified are the case temperature, the duration of the test, and the required hours to each down period. All tests are conducted at 15 volts unless otherwise specified

HIGH TEMPERATURE REVERSE BIAS (300)

The application of a bias in the reverse (blocking) direction of the main junction of a device under condition of steady state elevated temperature. The parameters specified are the applied voltage, the ambient elevated temperature, the duration of the test, treatment of the control element, and the required hours to each down period. This test may alternately be referred to as "Blocking Life, Reverse Bias, or HTRB"

HIGH TEMPERATURE GATE BIAS (400)

The application of bias in the forward and reverse modes to the gate and reference terminal of a device under conditions of elevated temperature. The parameters specified are the gate-reference junction bias, the ambient elevated temperature, treatment of unused elements, the duration of the test, and the required hours to each down period. The reference terminal of current devices are the source terminal for power MOS transistors, the emitter for IGBT devices, and the cathode main terminal for MCT devices.

STORAGE LIFE (500)

The application of elevated ambient temperature to the device under test by means of insertion into a chamber. The parameters specified are the ambient elevated temperature, the test duration and the required hours to each down period.

TEMPERATURE CYCLE (600)

The alternate exposure of the device under test to two different ambient temperatures. The test is accomplished in a system composed of two temperature chambers with individual control of temperature and a mechanism capable of transferring the sample between chambers. The parameters specified are the two temperature values, the dwell time at each temperature, the ambient dwell between the temperature extremes, the duration of the test in number of cycles, and the required number of cycles to each down period.

THERMAL SHOCK (700)

The alternate exposure to immersion in liquid baths at two different temperatures. The parameters specified are the two temperature levels, the dwell time in each temperature, the allowed maximum transfer time between baths, the duration of the test and the required number of cycles to each down period.

AUTOCLAVE (800)

The exposure to elevated temperature and pressure caused by the heating of de-ionised water in a closed vessel. The parameters specified are the temperature (a function of the steam tables), the pressure, the test duration of the test, and the reqired hours to each down period.

RELATIVE HUMIDITY BIAS (900)

The exposure of the devices under test to an environment of elevated ambient temperature and elevated humidity under the influence of main junction bias. The parameters specified are the elevated temperature, the elevated humidity, the bias level, treatment of the control element, the duration of the test and the required hours to each down period.

STRESS MATRICES

Table 2.A Surgector
Stress/Duration	Plastic
HTRB(Blocking) 168/500/1000 hrs	VDRX=Rated Voltage TA=150OC,
Storage Life 168/500/1000 hrs	TA=150OC,
Temperature Cycle 500/1000 cycles	-65OC, +150OC, Air-to-Air
Thermal Shock 500/1000 cycles	-65OC, +150OC, Liquid-to- Liquid
Autoclave 96 hrs	TA=121OC, P=15psig
Relative Humidity Bias 168/500/1000 hrs	TA=85OC, 85% RH, Vds=80%
Transient Peak Surge	Rated ITM

 

Surgector
Parameter	End of Life Limit @ Standardized Cond.
IDRR/IDRM	Group A
VON	Group A
IHO	Group A
IGT	Group A
VT	Group A

 

Table 3.A Rectifier
	Plastic	Hermetic
Power Cycle 10000/20000cy(Herm) 3000/6000cy(Plastic)	IF = Rated (Ave..) D TC = 100OC		IF = Rated (Ave) D TC = 100OC
HTRB(Blocking) 168/500/1000 hrs	Rated VDRX TA=175OC		Rated VDRX TA=175OC
Storage Life 168/500/1000 hrs	TA=200OC		TA=200OC
Temperature Cycle 500/1000 cycles	-65OC, +150OC, Air-to-Air		-65OC, +150OC, Air-to-Air
Thermal Shock500/1000 cycles	65OC, +150OC, Liquid-to-Liquid		Not required
Autoclave 96 hrs	TA=121OC, P=15PSIG		Not required
Relative Humidity Bias 168/500/1000 hrs	TA=85OC, 85% RH, Vcb=80%		Not required

 

Rectifier
Parameter	End of Life Limit @ Standardized Cond.>	Special Conditions
IR	Group A
VF	Group A
Hermeticity	1x10-8 atm/cc Fine No Bubbles Gross	Apply to hermetic devices only.
Intermittent Operation	No blinking light or electronic detect	Apply to Power Cycling test only. Must be confirmed by IF on curve tracer

 

Table 4.A Power Mos, IGBT
Stress/Duration	TO-3	4/8 Pdip	TO-39
Power Cycle 10000/20000 cycles	PD=56W, D TC = 50OC ID=2Amp		PD=2W, D TC =70OC ID=0.2Amp
Power Cycle 3000/6000 cycles> Extend to 20k cy for wearout		PD=1.5W, D TC = 70OC ID=0.5Amp
Operating Life 168/500 hrs	TCASE=200OC, VDS=15	TCASE=150OC, VDS15	TCASE=180OC, VDS=15
HTRB(Drain Source) 168/500/1000 hrs	TA=150OC, VDS =80%	TA=150OC, VDS=80%	TA=150OC, VDS=80%
HTRB(Gate Source) 168/500/1000 hrs	TA=150OC, VGS=100%	TA=150OC, VGS=100%	TA=150OC, VGS=100%
Storage Life 168/500/1000 hrs	TA=200OC	TA=150OC	TA=200OC
Temperature Cycle 500/1000 cycles	-65OC, +150OC, Air-to-Air	-65OC, +150OC, Air-to-Air	-65OC, +150OC, Air-to-Air
Thermal Shock 500/1000 cycles		65OC, +150OC, Liquid-to-Liquid

 

Table 4.B Power MOS, IGBT - Standard
Stress/Duration	TO-220/262/ SOT-186	TO-218/247	TO-251/237	TO-202
Power Cycle 3000/6000 cycles, Extend to 20k cy for wearout	PD=4.75W, D TC = 125OC ID=1Amp	PD=40W, D TC = 100OC, ID=2Amp	PD=2.5W, D TC = 125OC ID=.5Amp	PD=1.5W, D TC = 125OC ID=.5Amp
Operating Life 168/500 hrs	TCASE=200OC, VDS=15	TCASE=200OC, VDS=15V	TCASE=200OC, VDS=15V	TCASE=200OC, VDS=15V
HTRB(DS) 168/500/1000 hrs	TA=150OC, VDS=80%	TA=150OC, VDS=80%	TA=150OC, VDS=80%	TA=150OC, VDS=80%
HTRB(GS) 168/500/1000 hrs	TA=150OC, VGS=100%	TA=150OC, VGS=100%	TA=150OC, VGS=100%	TA=150OC, VGS=100%
Storage Life 168/500/1000 hrs	TA=200OC	TA=200OC	TA=200OC	TA=200OC
Temperature Cycle 500/1000 cycles	-65OC, +150OC, Air-to-Air	-65OC, +150OC, Air-to-Air	-65OC, +150OC, Air-to-Air	-65OC, +150OC, Air-to-Air
Thermal Shock 500/1000 cycles	-65OC, +150OC, Liquid-to-Liquid	-65OC, +150OC, Liquid-to-Liquid	-65OC, +150OC, Liquid-to-Liquid	-65OC, +150OC, Liquid-to-Liquid
Autoclave 96 hrs	TA=121OC, P=15psig	TA=121OC, P=15psig	TA=121OC, P=15psig	TA=121OC, P=15psig
Relative Humidity -bias 168/500/1000 hrs	TA=85OC, 85% RH, VDS=80%	TA=85OC, 85% RH, VDS=80%	TA=85OC, 85% RH, VDS=80%	TA=85OC, 85% RH, VDS=80%

 

Table 4.C Power MOS - Low Voltage Megafet
Stress/Duration	TO-220/262/ SOT-186	TO-218/247	TO-251/237	TO-202
Power Cycle 3000/6000 cycles, Extend to 20k cy for wear-out	PD=4.75W, D TC = 125OC ID=1Amp	PD=40W, D TC = 100OC ID=2Amp	PD=2.5W, D TC = 125OC ID=.5Amp	PD=1.5W, D TC = 125OC ID=.5Amp
Operating Life 168/500 hrs	TCASE=200OC, VDS=15	TCASE=200OC, VDS=15V	TCASE=200OC, VDS=15V	TCASE=200OC, VDS=15V
HTRB(DS) 168/500/1000 hrs	TA=175OC, VDS=80%	TA=175OC, VDS=80%	TA=175OC, VDS=80%	TA=175OC, VDS=80%
HTRB(GS) 168/500/1000 hrs	TA=175OC, VGS=100%	TA=175OC, VGS=100%	TA=175OC, VGS=100%	TA=175OC, VGS=100%
Storage Life 168/500/1000 hrs	TA=200OC	TA=200OC	TA=200OC	TA=200OC
Temperature Cycle 500/1000 cycles	-65OC, +150OC, Air-to-Air	-65OC, +150OC, Air-to-Air	-65OC, +150OC, Air-to-Air	-65OC, +150OC, Air-to-Air
Thermal Shock 500/1000 cycles	-65OC, +150OC, Liquid-to-Liquid	-65OC, +150OC, Liquid-to-Liquid	-65OC, +150OC, Liquid-to-Liquid	-65OC, +150OC, Liquid-to-Liquid
Autoclave 96 hrs	TA=121OC, P=15psig	TA=121OC, P=15psig	TA=121OC, P=15psig	TA=121OC, P=15psig
Relative Humidity -bias 168/500/1000 hrs	TA=85OC, 85% RH, VDS=80%	TA=85OC, 85% RH, VDS=80%	TA=85OC, 85% RH, VDS=80%	TA=85OC, 85% RH, VDS=80%

 

MOSFET
Parameter	End of Life Limit @ Standardized Cond.	Special Conditions
IDSX	Group A
IGSS,IGSSR	Group A
VTH	Group A	and: Delta of -0.3 volts
VDSV	Group A	or: Delta <= 40% whichever is greater.
BVDSX	Group A
Theta JC	Group A (Notes 1 & 2)	Only applies to cycling tests
Hermeticity	1x10-8 atm/cc Fine No Bubbles Gross	Apply to hermetic devices only.
Intermittent Operation	No blinking light or electronic detect	Apply to Power Cycling test only.

 

IGBT
Parameter	End of Life Limit @ Standardized Cond.	Special Conditions
ICES	Group A
IGES/IGES	Group A
VGETH	Group A	and: Delta of -0.3 volts
VCEON	Group A	or: Delta <= 40% whichever is greater.
BVCES	Group A
Theta JC	Group A (Notes 1 & 2)	Only applies to cycling tests
Hermeticity	1x10-8 atm/cc Fine, No Bubbles Gross	Apply to hermetic devices only.
Intermittent Operation	No blinking light or electronic detect	Apply to Power Cycling test only.

 

APPENDIX A

DEFINITION OF TERMS
Chi Square	A distribution related to the variance of samples taken from a normal distribution.
Class Action	The reliability acceptance of a device based on its similarity to a previously qualified device.
CONSTRUCTION ANALYSIS	A description of the fabrication details of a power device die.
DESIGN VERIFICATION	Very early samples of a new design intended to confirm the ability of the design to meet its performance objectives.
DESIGN REVIEW	A meeting whose purpose is to inform the various organizations of the proposed design for a power device
Die Fracture	A crack in a semiconductor die caused by the application of stress.
Factory Transfer	The transfer of a device from the device development activity to production.
FAILURE MECHANISM	A description of the means by which something fails.
FAILURE RATE	The number of failures occurring per unit time. Generally accepted to be related to the constant failure rate or useful life portion of a device life cycle.
FAILURE MODE	Physical description of a failure indicator.
FIT	Failure in time. The number of failures occurring in 10E9 hours. Obtained by multiplying per cent per 1000 hours by 10E4
FMEA	Failure Modes and Effects Analysis .The process of analyzing the potential failure modes and effects of a design or process.
Group "A" Parameters	A classification of semiconductor parameters routinely measured by the manufacturer to insure compliance with databook specification.
High Pot	High potential testing intended to evaluate the isolation capability of isolated packages.
IGBT	Insulated Gate Bipolar Transistor. Combines the best features of the bipolar transistor with the high impedance gate of MOS transistors.
LTPD	Lot tolerance per cent defective from MIL STD 750.
MCT	MOS Controlled Thyristor. A family of thyristor like devices with conduction controlled by an MOS gate.
Mobile Ionics	Ions which are free to migrate usually under the influence of some stress. In the semiconductor sense these are undesirable contaminants which adversely affect device performance.
Non-Accepted product	Product not officially accepted by the reliability qualification process.
Parametric Degradation	Any undesirable shift in the parameters of a device under test.
PER CENT/1000 HOURS	Unit for expressing failure rate. Obtained by multiplying the failure rate by 10E5
POWER DEVICE	Any of a number of families of solid state transistor products generally distinguished by power ratings > 1 watt.
PROCESS	For the purposes of this document, the division of power device technologies into groups according to the method of fabrication.
RELIABILITY	The ability of a device to perform its intended function for a specified period of time.
STRESS	The application of conditions to a device or structure which causes permanent or temporary changes to its physical characteristics.
TECHNOLOGY	For the purposes of this document, the categorization of power devices by function.
TEST PLAN	A listing of the tests, sample sizes, number of lots, etc. required for reliability acceptance.