Reliability Approach

Fairchild utilizes both traditional reliability test methods and Wafer Level Reliability (WLR) test techniques to assess product reliability  during qualification testing. A properly designed qualification sequence exposes, within a matter of days or weeks, those design, materials, or workmanship weaknesses  which could lead to device failure in the customer's application after months or even years in operation. All of our test methods are based on customer requirements and current industry standards and are fully documented. A summary table detailing traditional reliability test procedures (for plastic packages) utilized by Fairchild Semiconductor appears below:

In addition to these traditional reliability stresses, Fairchild has an active Wafer Level Reliability (WLR) program that serves to assess process reliability by providing quantifiable data on failure rate by mechanism (i.e.; mobile ionics) using very quick (typically less than one minute), highly accelerated stress techniques. These non-traditional stress techniques are meant to provide supplementary data to the traditional stress techniques for the purposes of characterizing and improving process reliability during the development stage. Fairchild has developed WLR tests for the following failure mechanisms:

• Intermetal Dielectric Integrity
• Metal Step Coverage
• Mobile Ionics
• Metal Stress Voids
• Gate Oxide Integrity
• Passivation Integrity
• Hot Electron Degradation
• Metal Electromigration