NDS332P

P-Channel Logic Level Enhancement Mode Field Effect Transistor

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics,     and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

Features

  • -1 A, -20 V, RDS(ON) = 0.41Ω @ VGS= -2.7 V, RDS(ON) = 0.3 Ω @ VGS = -4.5 V.
  • Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.0V.
  • Proprietary package design using copper lead frame for superior thermal and electrical capabilities.
  • High density cell design for extremely low RDS(ON).
  • Exceptional on-resistance and maximum DC current capability.
  • Compact industry standard SOT-23 surface Mount package.
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Index Product Product &
Eco Status
Unit Price/
1K Order
Packing Method Convention Package Marking
Convention*
Qualification
Support
Compliance
Certificates
0 NDS332P Full Production
Green as of Dec 2011
$0.334

SSOT 3L -  Details
1.12 x 2.92 x 1.4mm,  TAPE REEL

PDF SSOT 3L  Drawing
Last Update: Jan 2015 PDF SSOT-3L Packing Drawing
Last Update: Jan 2015
Line 1&E (Space)
&Y (Binary Calendar Year Coding)

Line 2332&E (Space)
&G (Weekly Date Code)

FIT 5.8

ESD (CDM) 1500V

ESD (HBM) 100V

RƟJA 250°C/W

RƟJC 75°C/W

Moisture Sensitivity Level (MSL) 1

Max Reflow Temp 260

PDF RoHS IPC1752
XML RoHS IPC1752
PDF RoHS/REACH/JIG

If there is no sample button displayed at the top of the page, please contact one of the Fairchild distributors or your local sales office to obtain samples.
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This product is general usage and suitable for many different applications.
Application Note Description
AN-7533 PDFA Revised MOSFET Model With Dynamic Temperature Compensation
Last Update : 05-Mar-2011
AN-9065 PDFFRFET® in Synchronous Rectification
Last Update : 28-Jun-2014
AN-4163 PDFShielded Gate PowerTrench® MOSFET Datasheet Explanation
Last Update : 23-Oct-2014
AN-558 PDFIntroduction to Power MOSFETs and their Applications
Last Update : 28-Jun-2014
AN-7510 PDFA New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options
Last Update : 05-Mar-2011
AN-9005 PDFDriving and Layout Design for Fast Switching Super-Junction MOSFETs
Last Update : 26-Nov-2014
AN-9010 PDFMOSFET Basics
Last Update : 09-Sep-2013
AN-7515 PDFA Combined Single-Pulse and Repetitive UIS Rating System
Last Update : 03-Mar-2011
AN-9034 PDFPower MOSFET Avalanche Guideline
Last Update : 05-Mar-2011
Package Condition Temperature Range Vcc Range Software Version Revision Date
PSPICE
SSOT 3L Electrical 25°C to 125°C N/A OrCAD 16.3 28-Feb-2012

For additional information please visit the Models page.

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